The present invention relates to integrated circuit memory devices, and in particular to content addressable memory (CAM) arrays.
Conventional random access memory (RAM) arrays include RAM cells (e.g., static RAM (SRAM) cells, dynamic RAM (DRAM) cells, and non-volatile RAM (NVRAM) cells) that are arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells within the RAM array. A data word is typically written into a RAM array by applying physical address signals to the RAM array input terminals to access a particular group of RAM cells, and applying data word signals to the RAM array input terminals that are written into the accessed group of RAM cells. During a subsequent read operation, the physical address of the group of RAM cells is applied to the RAM array input terminals, causing the RAM array to output the data word stored therein. Groups of data words are typically written to or read from the RAM array one word at a time. Because a relatively small portion of the entire RAM array circuitry is activated at one time to perform each data word read/write operation, a relatively small amount of switching noise within the RAM array, and the amount of power required to operate a RAM array is relatively small.
In contrast to RAM arrays, content addressable memory (CAM) arrays include memory cells (e.g., SRAM cells, DRAM cells, or NVRAM cells) in response to their content, rather than by a physical address. Specifically, a CAM array receives a data value that can be compared with all of the data words stored in the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. Because large amounts of data can be searched at one time, CAM arrays are often much faster than RAM arrays in certain systems, such as search engines.
While CAM arrays are faster than RAM arrays in performing search functions, they consume significantly more power and generate significantly more switching noise than RAM arrays. In particular, in contrast to RAM arrays in which only a small portion of the total circuitry is accessed during each read and write operation, significantly more power is needed (and noise is generated) in a CAM array because a relatively large amount of circuitry is accessed during each lookup operation.
To reduce the total power consumed by CAM arrays, there is a trend toward producing CAM arrays that operate on low system voltages. To facilitate lower voltages, the integrated circuit (IC) fabrication technologies selected to produce such CAM arrays utilize smaller and smaller feature sizes. In general, the smaller the feature size of an IC, the lower the system voltage that is used to operate the IC. However, when IC feature sizes and system voltages are reduced too much, the amount of charge stored at each node within the CAM array becomes so small that a soft error problem arises, which is discussed below with reference to FIG. 1.
FIG. 1 is a simplified cross sectional view showing an N-type diffusion (node) 50 formed in P-type well (P-WELL) 51, which is exemplary of a typical IC feature (e.g., a drain junction utilized to form an N-type transistor). Dashed line capacitor 52 represents the capacitance of node 50, and indicates that node 50 stores a positive charge.
As indicated in FIG. 1, if an energetic particle, such as an alpha-particle (xcex1), from the environment or surrounding structure strikes the N-type diffusion of node 50, then electrons (e) and holes (h) will be generated within the underlying body of semiconductor material (i.e., in P-well 51). These free electrons and holes travel to the node 50 and P-well 51, respectively, thereby creating a short circuit current that reduces the charge stored at node 50. If the energy of the alpha-particle is sufficiently strong, or if the capacitance 52 is too small, then node 50 can be effectively discharged. When node 50 forms a drain in an SRAM cell and the charge perturbation is sufficiently large, the stored logic state of the SRAM cell may be reversed (e.g., the SRAM cell can be flipped from storing a logic xe2x80x9c1xe2x80x9d to a logic xe2x80x9c0xe2x80x9d). This is commonly referred to as a xe2x80x9csoft errorxe2x80x9d because the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten).
Soft errors also arise due to other mechanisms, such as switching noise. As discussed above, switching noise is significantly higher in CAM arrays than in conventional RAM arrays, thereby making the problem of soft errors even greater in CAM arrays.
Many approaches have been proposed for dealing with soft errors, such as increased cell capacitance or operating voltage, and error detection schemes (such as using one or more parity bits). While these proposed approaches are suitable for standard RAM arrays, they are less desirable in CAM arrays. As pointed out above, CAM arrays inherently consume more power than RAM arrays. Therefore, while increased cell size and/or operating voltage can be tolerated in a RAM array, such solutions are less desirable in a CAM arrays. Moreover, adding error detection schemes to CAM arrays increase the size (and, hence, the cost) of the CAM arrays, and further increase power consumption.
Accordingly, what is needed is a memory system that addresses the soft error problem associated with a CAM array of the system without greatly increasing the cost and power consumption of the CAM array.
The present invention is directed to a memory circuit including a CAM array, a RAM array, and a control circuit that coordinates the operation of the CAM array and RAM array such that data stored in the CAM array is systematically refreshed using data read from the RAM array. The control circuit receives operation requests (e.g., read, write, or lookup (search) operations), and transmits corresponding data and/or control signals to the RAM and CAM arrays. In accordance with an aspect of the present invention, data values written to selected CAM cells of the CAM array are also written to corresponding memory cells of the RAM array. Subsequently, the control circuit systematically refreshes the selected CAM cells by reading the data values from the corresponding memory cells of the RAM array, and then writing the data values to the corresponding CAM cells. By frequently refreshing the CAM array using data read from the RAM array, soft errors in the CAM array are essentially eliminated because erroneous data values arising from, for example, alpha-particle strikes, are immediately corrected during the next refresh operation. Further, because the present invention avoids the need to incorporate a soft error prevention scheme into the CAM array, the cost of fabricating the CAM array is reduced.
In accordance with another aspect of the present invention, during data read operations, data values are only read from the RAM array (i.e., not from the CAM array). By reading data values only from the RAM array, operation of the CAM array is greatly simplified. Lookup operations are preformed by the CAM array in a conventional manner.
In accordance with alternative embodiments of the present invention, the memory circuit is integrally fabricated on a single substrate (e.g., silicon chip), or the CAM and RAM arrays are fabricated as separate devices that communicate through interface circuits. When the RAM array is designed using a soft error prevention scheme that utilizes parity bits and the memory cells in the CAM and RAM arrays are the same size, then the RAM and CAM arrays may be fabricated on a single chip to minimize assembly costs. However, when the RAM array utilizes a soft error prevention scheme based on high voltage and/or larger cell capacitance (i.e., the memory cell size of the RAM array is larger than the memory cells utilized in the CAM array), then the RAM and CAM arrays may be beneficially fabricated on separate chips to minimize fabrication costs. Further, fabricating the CAM array and RAM array separately may significantly increase fabrication yields, thereby reducing the total cost of the memory circuit. In one embodiment utilizing separate chips for the CAM and RAM arrays, the separate chips are mounted in a single package and connected, for example, using a flip-chip arrangement. In another embodiment, the CAM array and RAM array chips are separately packaged and connected via conductive traces formed on a printed circuit board.
In accordance with another aspect of the present invention, binary, ternary, and quad (four state) CAM circuits are implemented by combining binary or ternary CAM arrays with appropriately sized RAM arrays. In one example, a 9 Megabyte binary CAM array is combined with a 9 Megabyte RAM array to produce a binary CAM circuit that stores logic xe2x80x9c1xe2x80x9d or logic xe2x80x9c0xe2x80x9d data values in each CAM cell in accordance with corresponding data stored in an associated memory cell of the RAM array. In another example, a 9 Megabyte ternary CAM array is combined with an 18 Megabyte RAM array (or two 9 Megabyte RAM arrays) to produce a ternary CAM circuit that stores a logic xe2x80x9c1xe2x80x9d, a logic xe2x80x9c0xe2x80x9d, or a xe2x80x9cdon""t carexe2x80x9d data value in each CAM cell in accordance with corresponding data stored in an associated pair of memory cells of the RAM array. In yet another example, a quad CAM circuit is implemented using a 9 Megabyte CAM array, which is modified to include a translation circuit, and an 18 Megabyte RAM array (or two 9 Megabyte RAM arrays). The translation circuit writes a logic xe2x80x9c1xe2x80x9d or a logic xe2x80x9c0xe2x80x9d on in the ternary CAM cell in accordance with a data value stored in an associated first memory cell of the RAM array when an associated second (mask) memory cell of the RAM array indicates a xe2x80x9cno maskxe2x80x9d state. Conversely, when the second memory cell indicates a xe2x80x9cmaskxe2x80x9d state, the translation circuit writes a xe2x80x9cdon""t carexe2x80x9d data value into the associated ternary CAM cell no matter what data value is stored in the first memory cell. Accordingly, the data value (logic xe2x80x9c1xe2x80x9d or logic xe2x80x9c0xe2x80x9d) for each CAM cell is retained in the RAM array even when the data value is masked in the CAM array.
In accordance with another aspect of the present invention, the CAM array and PAM array may store data values using memory cells that are based on the same or different cell types. For example, the CAM array and RAM array may both utilize SRAM memory cells to store data values, or both include DRAM memory cells. Alternatively, the CAM array may utilize SRAM memory cells and the RAM array may utilize DRAM memory cells, or the CAM array may utilize DRAM memory cells and the RAM array utilize SRAM memory cells. Moreover, one or both of the CAM and RAM memory cells may include an EEPROM or any other type of non-volatile memory cells.
The present invention will be more fully understood in view of the following description and drawings.